Innovative Applications of Nanowires for Circuit Design by Raj Balwinder

Author:Raj Balwinder
Language: eng
Format: epub
Publisher: Engineering Science Reference

Nanowire FETs

In NWFET device channel is consist of nanowire having diameter in nanometer. Si based NWFET devices are difficult to fabricated, so a lot of attention has been placed on homogenous Si based NWFETs and III-V NWFETs have been introduced because these materials have superb carrier transport. NWFET have many benefits over conventional CMOS devices as (Iwai et al., 2009). Firstly, NW based devices have capability to reduced SCEs, low OFF-current (IOFF), due to Gate all around structure. Secondly, NW based devices have high ON-current (ION) because of quasi One Dimensional (1D) conduction of NWs. Due to 1D transport in nanowire conduction is very high and less carrier scattering (Sakaki, 1980). The band structure of nanowire is different as compared planer device; the sub-bands seem close to lowest band in nanowire. These distinct sub bands enhance near the conduction band (Ohno et al., 1992). The fabrication steps of nanowire based FET is less as compare to conventional CMOS devices (Lauhon et al., 2002).

The Structures of Double-Material-Gate NWFET and Simulation Parameters

The structure of NWFET has been designed by using Silvaco ATLAS. Figure 2 shows the 3D and 2d cut section of Double-Material-Gate NWFET with device dimension. The device channel, source, drain length is 20 nm and Diameter (D) is 5 nm. The dielectric used is Hfo2 for high K and Sio2 for low k (Chaturvedi et al., 2014). The work function (ΦM1) of gate metal near source is 4.83eV and work function of metal at drain side is 4.41eV are used to get the preferred threshold voltage. The length of overall channel is equal to L=20(L1+L2). Thickness of SiO2 and HfO2 is 0.4nm and 2.1nm.The device structure parameters are given in table 2.

Figure 2. (a) 3D and (b) 2D cut plane view of Double-Material-Gate NWFET

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